Digitally Controlled Delay lines Using Strobe Controlled Logic

Vol.2  No.1

Year : 2014

Issue : Jan-Mar

Title : Digitally Controlled Delay lines Using Strobe Controlled Logic

Author Name : manimekalai n, A. Lelinadevi

Synopsis :

In recent years, Digitally Controlled Delay-Lines (DCDL) is a key block in number of applications and play the role of DAC in traditional circuits. This paper presents a totally glitch free DCDL which overcame the limitation of a NAND based DCDL using strobe control method. Using this logic a clock is presented, that reduces the output jitter when compared to the existing method. The existing method uses a delay control code and reduces the delay of about 40%, but it consumes more power and less area efficient. By using strobe controlled logic, the peak to peak absolute output jitter of 70-80% were reduced. As an example application, All-digital spread-spectrum clock generator (SSCG), All-digital phase-locked loops (ADPLL), Phase-locked loop (PLL) were used.

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