Automatic Traffic Management System for Emergency Vehicles

Volume 7 Issue 1 January - March 2019

Technical Column

Automatic Traffic Management System for Emergency Vehicles

Jamuna*, Vinay M. G.**

*-** Department of Computer Science and Engineering, Vidyavardhaka College of Engineering, Mysuru, Karnataka, India.

Jamuna and Vinay, M. G., (2019). Automatic Traffic Management System for Emergency Vehicles. i-manager’s Journal on Digital Signal Processing, 7(1), 36-42.

Abstract

One of the major problems faced by people in their daily life is traffic. An efficient management system is required to provide efficient traffic control system. Identification of particular vehicle in the traffic flow is a notable task in the traffic management system. In this project, we propose an automatic traffic management system for vehicle detection and counting and automatic signals scheduling. The camera supplies video input to the processing engine. Initially the video will be streaming on all four roads of the traffic circle. The values will be read frame by frame in the streaming video of these roads. Camera sends all the captured input images to the processing engine and this works based on the neural network. The traffic flow shows the traffic state in fixed time interval and helps to manage and control the traffic especially when there is a heavy traffic and will consider emergency vehicles like ambulance and fire brigades, giving them priority togo.

FPGA Based Implementation of Median Filter using Compare and Exchange Unit

Volume 7 Issue 1 January - March 2019

Research Paper

FPGA Based Implementation of Median Filter using Compare and Exchange Unit

Srinu Boni*, Srinu Bevara**, Nagendra Kumar. M***

* Department of Electronics and Communication Engineering, Lendi Institute of Engineering and Technology, Vizianagaram, Andhra Pradesh, India.

** Department of Electronics and Communication Engineering, Gayatri Vidya Parishad College of Engineering (Autonomous), Visakhapatnam, Andhra Pradesh, India.

*** Department of Electronics and Communication Engineering, MVGR College of Engineering(A), Vizianagaram, Andhra Pradesh, India.

Boni, S., Bevara, S., & Kumar, N. M. (2019). FPGA Based Implementation of Median Filter using Compare and Exchange Unit i-manager’s Journal on Digital Signal Processing, 7(1), 31-35.

Abstract

Over the past few years, so many new so- lutions are gaining popularity in the software industry. All these solutions require a fast and parallel data manipulation. An attempt has been made to design median filter with high throughput and good latency to suppress the impulse based noise on real time signal and image processing applications. It is partially affected by the median filter and its bias of the input stream is directly above the average of mathematical analysis. An efficient VLSI suitable hardware implementation of a median filter is presented, that uses compare and exchange unit. The proposed hardware structure reduces the hardware requirements and has a faster processing speed, when com- pared with some other existing techniques. The input numbers or streams are used to construct an algorithm. By using this algorithm to find the median number. The proposed technique can be implemented with perfect shuffle interconnects between active stages of compare and exchange elements. In this paper all the designs are synthesized and created using MAX PLUS- II from ALTERA with fmax = 486.38MHz.

Developing Sidelobe Reduction Techniques using P4 Code for Pulse Compression Radar Applications

Volume 7 Issue 1 January - March 2019

Research Paper

Developing Sidelobe Reduction Techniques using P4 Code for Pulse Compression Radar Applications

CH. RamyaSree*, G.H. Sindhuja**, A.V. Sai Kumar***, G. Sri Harsha****, B. Kiranmai*****

*_***** Department of Electronics and Communication Engineering, Lendi Institute of Engineering and Technology, Vizianagaram, Andhra Pradesh, India.

Sree, R., Sindhuja, G. H., Kumar, A. V. S., Harsha, G. S., & Kiranmani, B. (2019). Developing Sidelobe Reduction Techniques using P4 Code for Pulse Compression Radar Applications i-manager’s Journal on Digital Signal Processing, 7(1), 25-30.

Abstract

This paper present a novel technique for the ‘reduction of the side-lobes in the pulse compression (PC)’ for the radar systems. This pulse compression increases the range resolution and signal to noise ratio. The peak sidelobe ratio and signal noise reduction loss are computed using P4 polyphase codes. This result is compared with various weighting techniques applied on the output of Woo filter in order to suppress the side lobes. This proposed PC technique is implemented by shifting the input P4 polyphase codes and multiplied it with reference signal. This technique produces certain improvement in Peak Sidelobe Ratio and Signal Noise Reduction Loss(SNR Loss).

Speed Enhancement of Modified Booths Encoding Algorithm Using Verilog HDL

Volume 7 Issue 1 January - March 2019

Research Paper

Speed Enhancement of Modified Booths Encoding Algorithm Using Verilog HDL

Gopi Chand Naguboina*, T. Sravya**

* Department of Electronics and Communication Engineering, MVGR College of Engineering(A), Vizianagaram, AndhraPradesh India.

** Department of Electrical and Electronics Engineering, Lendi Institute of Engineering and Technology, Vizianagaram, AndhraPradesh, India.

Naguboina, G. C., & Sravya. T. (2019). Speed Enhancement of Modified Booths Encoding Algorithm Using Verilog HDL. i-manager’s Journal on Digital Signal Processing, 7(1), 20-24.

Abstract

This paper presents the design and implementation of Modified Booths encoding algorithm with enhanced speed. Multiplication is the most commonly used operation in every step of arithmetic. The speed of multiplier determines the speed of processor. So, there is a need for high speed multiplier. Adders play a dominant role in arithmetic addition of partial products. Increase in the speed of any arithmetic operation results in the increase of speed of overall operation of multiplier. So the main focus in this paper is to increase the speed of adder in turn increasing the speed of multiplication process. An algorithm is proposed using Modified Booths algorithm, Wallace tree structure and Kogge-Stone adder design. MBE reduces the number of partial products and has least latency compared to other multiplier algorithms. Wallace tree structure increases the speed of accumulation of partial products. A Kogge-Stone adder design is used in the multiplier design which yields to reduced delay and area. The proposed Modified Booth Multiplier design shows better performance compared to that of the conventional method using Kogge-Stone Adder and has advantages of reduced area overhead and critical path delay. The proposed design has been synthesized using Xilinx ISE 14.2 design tool using Verilog HDL.

Design of Y Shaped 2x1 Encoder using Two Dimensional Photonic Crystals

Volume 7 Issue 1 January - March 2019

Research Paper

Design of Y Shaped 2x1 Encoder using Two Dimensional Photonic Crystals

K. Latha*, R. Arunkumar**, S. Robinson***

*_*** Department of Electronics and Communication and Engineering, Mount Zion College of Engineering and Technology, Pudukkottai, Tamilnadu, India.

Latha, K., Arunkumar, R., & Robinson, S. (2019). Design of Y Shaped 2x1 Encoder using Two Dimensional Photonic Crystals. i-manager’s Journal on Digital Signal Processing, 7(1), 11-19.

Abstract

In this Y shaped 2x1 encoder design is based on two dimensional photonic crystals. And this encoder design is constructed by point and line defects of photonic crystal which is providing high contrast ratio and reduced power loss for proposed design. The performances field distributions are analyzed finite difference time domain and the band structures are evaluated plane wave expansion method. The proposed 2x1 encoder operated at 1520nm and it provides contrast ratio of 28dB, response time of 3.9ps and bit rate of around 0.25Tbps. So, it is suitable for photonic integrated circuits.

Airbase Detection and Airship Recognition in High Spatial Resolution Remote Sensing Images

Volume 7 Issue 1 January - March 2019

Research Paper

Airbase Detection and Airship Recognition in High Spatial Resolution Remote Sensing Images

B. Bersi Beulah*

Department of Electronics and Communication and Engineering, PET Engineering College, Tirunelveli, Tamil Nadu, India.

Beulah, B. B. (2019). Airbase Detection and Airship Recognition in High Spatial Resolution Remote Sensing Images. i-manager’s Journal on Digital Signal Processing, 7(1),1-10.

Abstract

In the proposed work two-layer visual saliency analysis model and support vector machines (SVMs) are used for Airport detection and Aircraft Recognition. In the first layer saliency (FLS) model, introduce a spatial-frequency visual saliency analysis algorithm that is based on a CIE Lab color space to reduce the interference of backgrounds and efficiently detect well-defined airport regions in broad-area remote-sensing images. In the second layer saliency model, propose a saliency analysis strategy that is based on an edge feature preserving wavelet transform and high-frequency wavelet coefficient reconstruction to complete the preextraction of aircraft candidates from airport regions that are detected by the FLS and crudely extract as many aircraft candidates as possible for additional classification in detected airport regions. Then, utilize feature descriptors that are based on a dense SIFT and Hu moment to accurately describe these features of the aircraft candidates. Finally, these object features are inputted to the SVM, and the aircraft are recognized. The experimental results indicate that the proposed method not only reliably and effectively detects targets in high-resolution broad-area remotesensing images but also produces more robust results in complex scenes.

Internet of Things (IoT) Based Home Automation: A Review

Volume 6 Issue 4 October - December 2018

Review Paper

Internet of Things (IoT) Based Home Automation: A Review

Nidhi Singh*, Ankita Sharma **, Anurag Dwivedi ***, Nitesh Tiwari ****

*-**** Department of Electrical Engineering, KIPM College of Engineering & Technology, Gorakhpur Industrial Development Authority, Gorakhpur, Uttar Pradesh, India.

Singh, N., Sharma, A., Dwivedi, A., and Tiwari, N. (2018). Internet of Things (IoT) Based Home Automation: A Review. i-manager’s Journal on Digital Signal Processing, 6(4), 34-41. https://doi.org/10.26634/jdp.6.4.15955

Abstract

The recent decade has experienced revolution of smart technology with the introduction of smartphones and electronic equipments in day to day life as an important part of life. IoT (Internet of Things) can be defined as human connecting object like sensors, internet TVs, smartphones and actuators with the internet where electronic devices are linked together intelligently enabling new shell of communication between people and electronic devices, and between devices themselves. IoT is presented with the overview to begin the idea of a smart home with its security and the necessity of software and hardware components for making a smart home.

Design and Analysis of all Optical Half Adder Based on Two Dimensional Photonic Crystals

Volume 6 Issue 4 October - December 2018

Research Paper

Design and Analysis of all Optical Half Adder Based on Two Dimensional Photonic Crystals

Rama Prabha K.*, Arun Kumar R. **, Robinson S. ***

*_*** Department of Electronics and Communication Engineering, Mount Zion College of Engineering and Technology, Pudukkottai, Tamilnadu, India.

Prabha, R. K., Kumar, R. A., and Robinson, S. (2018). Design and Analysis of all Optical Half Adder Based on Two Dimensional Photonic Crystals. i-manager’s Journal on Digital Signal Processing, 6(4), 27-33. https://doi.org/10.26634/jdp.6.4.16266

Abstract

In this paper the design and analysis of all optical half adder based on two dimensional photonic crystals is presented. A half adder is a type of adder, an electronic circuit that performs the addition of numbers. The half adder is able to add two single binary digits and provide the output plus a carry value. The proposed structure uses a hexagonal lattice with the point defect based structure. The structural design is small in size and it is compact in nature. These structural analysis of half adder mainly satisfies the logic function as A=1, B=0, A=0, B=1, A=1, B=1. The functional parameters of half adder such as normalized efficiency, bit rate, contrast ratio and the maximum delay time are calculated. The main application of half adder is to compute binary addition operation on two bits in integrated circuits.

VLSI Implementation of Low Power Image Transmission Employing Modified JSCC Scheme

Volume 6 Issue 4 October - December 2018

Research Paper

VLSI Implementation of Low Power Image Transmission Employing Modified JSCC Scheme

E. Kiruba Bethesthal Elizabeth*, S. P. Valan Arasu **

*-**Department of Electronics & Communication Engineering, VV College of Engineering, Tisaiyanvilai, Tirunelveli, Tamil Nadu, India.

Elizabeth, E, K, B., and Arasu, S. V.P. (2018). VLSI Implementation of Low Power Image Transmission Employing Modified JSCC Scheme. i-manager’s Journal on Digital Signal Processing, 6(4), 20-26. https://doi.org/10.26634/jdp.6.4.16263

Abstract

Forward error correction enables reliable one- way communication over noisy channels, by transmitting redundant data along with the message in order to detect and resolve errors at the receiver. Low-density parity-check (LDPC) codes achieve superior error-correction performance on Gaussian channels, however, their complex parity-check matrix structure introduces hardware implementation challenges. Quasi-cyclic (QC) low-density parity-check (LDPC) codes form an important subclass of LDPC codes. The encoding of these codes is traditionally done by multiplying the message vector with a generator matrix consisting of dense circulant submatrices. To reduce the encoder complexity a new scheme is introduced by making use of finite fourier transform .Making use of conjugacy constraints, low complexity architectures are developed for finite fourier and inverse transforms over subfields. In addition composite field arithmetic is exploited to eliminate the computations associated with message mapping and to reduce the complexity of Fourier transform. Since the proposed encoder has much improvement in power consumption and reduction in area than the conventional encoders, it is considered to be an efficient QC-LDPC encoder.

Design and Implementation of Neonate Health Condition Monitoring Device

Volume 6 Issue 4 October - December 2018

Research Paper

Design and Implementation of Neonate Health Condition Monitoring Device

Naregalkar Akshay Rangnath*

Department of EIE, VNR Vignana Jyothi Institute of Engineering & Technology, Hyderabad, India.

Rangnath, N. A. (2018). Design and Implementation of Neonate Health Condition Monitoring Device. i-manager’s Journal on Digital Signal Processing, 6(4), 14-19. https://doi.org/10.26634/jdp.6.4.16110

Abstract

As per the survey conducted by UNICEF in 2018, more than 6 lakh neonatal deaths occur in India which makes India to stand in the worst rank of 12 among 52 developing or undeveloped countries. Also, every day an average of 7,000 neonatal deaths occur worldwide. A new born baby can survive outside of the mother's womb with the help of baby incubator, provided the required environment to be maintained by incubator for premature baby to sustain. But in recent time, improper incubator design, short circuit in incubator, gas leakage inside the incubator has caused accidental deaths of premature babies. This paper deals with the low cost neonatal incubator system that monitors neonatal vital parameters like pulse rate, body temperature and incubator parameters like moisture, oxygen percentage and light intensity. These parameters are monitored and moisture, oxygen percentage and light intensity are controlled with proposed incubator. These parameters are also sent to the hospital staff through IoT (Internet of Things), so that immediate action can be initiated to take proper care of neonatal that ensures safety to the neonatal (infant's) life by maintaining incubator parameters as required. In this paper in addition to these, one more important feature is included that is phototherapy to treat jaundice in new born.

The Efficient Highway Management System: Illuminating Roads of Future

Volume 6 Issue 4 October - December 2018

Research Paper

The Efficient Highway Management System: Illuminating Roads of Future

Venu Gopal Reddipalli*, Anurag Korrm **, Aditya Vikram Shivhare ***, Vikas Dewangan ****, Aman Soni *****, Alka Mishra ******

*-****** Department of Electrical and Electronics, Bhilai Institute of Technology, Durg, Chhattisgarh, India.

Reddipalli, V. G., Korrm , A., Shivhare, A. V., Dewangan, V., Soni, A., and Mishra, A. (2018). The Efficient Highway Management System: Illuminating Roads of Future. i-manager’s Journal on Digital Signal Processing, 6(4), 7-13.https://doi.org/10.26634/jdp.6.4.15954

Abstract

The Efficient highway system here refers to upgraded version of the current Highway Management System. This paper presents a smart system model which is self-dependent, self-sustainable and can operate without any human intervention. The presented system is combination of four sub-systems. The aim of the first subsystem is to detect and compare the traffic density at traffic squares to maintain the continuous and smooth flow of traffic which solves the problem of current scenario due to predefined timer system. The second subsystem uses IR sensors and a night detector to manipulate street light when not required hence reduces the wastage of energy. Both above subsystems are controlled with the single Microcontroller. The third subsystem which contains charging points installing underneath the roads such that they can be charged wirelessly any time which overcome the drawback of electric vehicle to travel long time. The aim of fourth subsystem is to generate clean and green energy using speed bumps as a concept of Road Power Generation and solar panels which makes the system self-sustainability.

LabVIEW Based Real Time Monitoring System for Coal Mine Worker

Volume 6 Issue 4 October - December 2018

Research Paper

LabVIEW Based Real Time Monitoring System for Coal Mine Worker

Viswasmayee Priyadarsini*, Abhishek Verma**, Meghna Singh***, Shivani Netam ****, Dipty Chandrakar*****

*-***** Department of Electrical and Electronics Engineering, Bhilai Institute of Technology, Durg, Chhatisgarh, India.

Priyadarsini, V., Verma, A., Singh, M., Netam, S., and Chandrakar, D. (2018). LabVIEW Based Real Time Monitoring System for Coal Mine Worker. i-manager’s Journal on Digital Signal Processing, 6(4), 1-6. https://doi.org/10.26634/jdp.6.4.16096

Abstract

Coal mining is the process of extraction of coal. For this, the workers have to work in various dangerous conditions in the coal mine. Historically, coal mining has been a dangerous activity and the list of mining accidents is long one. A single, small accident can cause the death of the mine worker/workers. So, it is important to have a warning system. This research work deals with plan and expansion of a LabVIEW and microcontroller based monitoring system. In this project, a device used for continuous monitoring of the worker in coal mines is designed. In previous research work, the focus was on monitoring the environmental conditions of coal mines by using environmental sensors like gas sensor, humidity sensor , etc. But different person respond to the same environmental condition in different way. Therefore, the main focus of this study is to monitor the worker who has to deal with the abnormal conditions of coal mines. The research team used ECG sensor (AD8232) to note the electrical behaviour of heart. The device can monitor the heart rate, analyse the health condition of workers using LabVIEW software. The analysed data can be continuously monitored by the concerned authority in the control room. In case the worker is suffocating (in case of abnormal mining environment) then immediately a web page pop up. Labview continuously compares the sensed value with the predefined critical safety values and then gives the alert indication signal accordingly to the heartbeat rate of the worker.

MDT Based Infinite Impulse Response-Decimation Filter (IIR-DF) Design: An Efficient and Low Computational Cost Design Approach

Volume 6 Issue 3 July - September 2018

Research Paper

MDT Based Infinite Impulse Response-Decimation Filter (IIR-DF) Design: An Efficient and Low Computational Cost Design Approach

Dimple Sharma*, Vikas Soni**, Pankaj Jain***

* PG Scholar, Department of Electronics and Communication Engineering, Modi Institute of Technology, Kota, Rajasthan, India.

** Professor Cum Principal, Modi Institute of Technology, Kota, Rajasthan, India.

*** Associate Professor, Department of Electronics and Communication Engineering, Modi Institute of Technology, Kota, India.

Sharma, D., Soni, V., Jain, P. (2018). MDT Based Infinite Impulse Response-Decimation Filter (IIR-DF) Design: An Efficient and Low Computational Cost Design Approach, i-manager's Journal on Digital Signal Processing, 6(3), 33-44.https://doi.org/10.26634/jdp.6.3.15566

Abstract

In this paper, the Merged Delay Transformation approach has been employed in order to design Infinite Impulse Response-Decimation Filter (IIR-DF) and it has also been proved that this approach is an efficient approach for designing IIR-DF. In the proposed approach called as; MDT-IIR-DF, filtering followed by Sampling Rate Compression (decimation process) is obtained in a single stage instead of two separate stages as in conventional IIR Filters which in turn reduces the cost of computation in terms of number of multipliers per output samples. Two Examples have been included which show that the cost of computation for proposed approach; MDT-IIR-DF is low as compared to the cost of computation for various conventional Filters like: Polyphase FIR, Conventional IIR and Polyphase IIR, respectively. The proposed approach; MDT-IIR-DF is better computationally efficient in which the computational efficiency is increased by merging the M number of delay elements in recursive part together so that the current output can be directly computed from Mth old output. Magnitude and Phase Response of various MDT based IIR filters like; Butterworth, Chebyshev-I, Chebyshev-II and Elliptical flters have been compared with conventional Butterworth, Chebyshev-I, Chebyshev-II and Elliptical IIR filters (without MDT approach). The simulation results show that same magnitude and phase response for both (with and without MDT approach) filters i.e. the MDT based IIR-DF has close agreement with conventional IIR filter at low computational cost along with afficient architecture.

Railway Track Fault Monitoring System using Signal Processing Techniques

Volume 6 Issue 3 July - September 2018

Research Paper

Railway Track Fault Monitoring System using Signal Processing Techniques

B. Sridhar*, B. Sharmila Devi**, A. Lavanya***, B. Ghana Prasuna****, G. Prudhvi Raj*****

* Professor, Department of Electronics and Communication Engineering, Lendi Institute of Engineering and Technology, Vizianagaram, Andhra Pradesh, India.

**-***** UG Students, Department of Electronics and Communication Engineering, Lendi Institute of Engineering and Technology, Vizianagaram, Andhra Pradesh, India.

Sridhar, B., Devi, B. S., Lavanya, A., Prasuna, B. G., Raj, G, P. (2018). Railway Track Fault Monitoring System using Signal Processing Techniques, i-manager's Journal on Digital Signal Processing, 6(3), 24-32. https://doi.org/10.26634/jdp.6.3.15423

Abstract

This paper presents railway track fault monitoring approach using signal processing techniques operator-based on signal separation. The measured vibration signal is first pre-processed using the Kalman filtering to filter the noise imposed on the signal. A specific band of frequency is identified using Finite Impulse Response (FIR) filter then an operator-based signal separation approach, called null space pursuit (NSP), is applied to decomposing the signal into a series of subcomponents and residues in accordance with their characteristics. Subsequently, the selected subcomponent with the maximum kurtosis value is analyzed by the envelop spectrum to identified potential fault-related characteristic frequency components. Experimental studies from the signals observed from railway track during the motion of the train have verified the effectiveness of the present approach for railway track fault monitoring system.

Neuronal Logic Gates Realization using CSD Algorithm

Volume 6 Issue 3 July - September 2018

Research Paper

Neuronal Logic Gates Realization using CSD Algorithm

Lakshmi kiran Mukkara*, K. Venkata Ramanaiah**

* Research Scholar, Department of Electronics and Communication Engineering, YSR Engineering College of Yogi Vemana University, Kadapa, Andhra Pradesh, India.

** Head, Department of Electronics and Communication Engineering, YSR Engineering College of Yogi Vemana University, Kadapa, Andhra Pradesh, India.

Mukkara, L. K., Ramanaiah, K. V. (2018). Neuronal Logic Gates Realization using CSD Algorithm, i-manager's Journal on Digital Signal Processing, 6(3), 18-23. https://doi.org/10.26634/jdp.6.3.15244

Abstract

Any digital circuit is made with fundamental building blocks i.e. logic gates. Artificial Neural Networks (ANN) became an emerging area in various applications such as prediction problems, pattern recognition, and robotics and system identification due to its processing capabilities with parallel architecture. Realization of Boolean logic with neural networks is referred as neuronal logic. ANN computes faster as it requires of low and simple precision computations. Also, it requires economic and low precision hardware. Neural network contains more number of addition and multiplication processes. It is known that CSD algorithm computes faster than conventional or standard multipliers. In this paper, VLSI implementation of neuronal half adder with CSD algorithm is proposed and implemented in FPGA. The results are compared with that of conventional and vedic multiplier. It is observed that CSD algorithm provides lowest delay and low power consumption in comparison with vedic algorithm and conventional method but at the expense of minimum area.

Application of Geographic Information Systems in Creating Smart Campus Map of Federal University of Technology, Minna Bosso Campus

Volume 6 Issue 3 July - September 2018

Research Paper

Application of Geographic Information Systems in Creating Smart Campus Map of Federal University of Technology, Minna Bosso Campus

M. O. Odekunle*, E. K. Odo**, I. Sule***, A. A. Adenle****

*,***-**** Lecturer, Department of Geography, Federal University of Technology, Minna, Nigeria.

** Student, Department of Geography, Federal University of Technology, Minna, Nigeria.

Odekunle, M. O., Odo, E. K., Sule, I., Adenle, A. A. (2018). Application of Geographic Information Systems in Creating Smart Campus Map of Federal University of Technology, Minna Bosso Campus, i-manager's Journal on Digital Signal Processing, 6(3), 10-17. https://doi.org/10.26634/jdp.6.3.15680

Abstract

The research work aimed at creating a smart campus map of Federal University of Technology, Bosso Campus, Minna, Niger State, Nigeria. The advancement of technology with an attendant emergence of digital maps is gradually phasing out obsolete paper maps. One of the problems inherent with paper maps is the difficulty visitors face in navigating the campus. The study utilized ArcGIS as the main digital mapping software. It was used for digitization and simulation of map features. Google Earth pro 7.1 was used to extract and download satellite image of Bosso campus, which was georeferenced to have the actual earth projection of the campus. The procedures employed include digitization, assignment of attributes to features, creation and editing of the map and finally, conversion of the map to KML format (the format that can be read by ArcGIS software), the utilization of Android Studio as an interactive software. The converted map is imported and overlaid with Google API 21. The Smart map is an interactive software between users and various objects in the visual environment, which further provides great convenience for the users to understand geographical environment and campus information of Bosso campus. The study demonstrates the potentials of digital mapping using GIS software and Android Studio in creating and managing spatial data. Smart digital map can be used as a tool to formulate development plans not only in the campus, but also for wider coverage areas.

Examination Eligibility Verification and Attendance System Using Quick Response Code

Volume 6 Issue 3 July - September 2018

Research Paper

Examination Eligibility Verification and Attendance System Using Quick Response Code

Muhammad Bashir Abdullahi*, Zahra’u Musa Nura**, Lawal Musa Jiya***

*-*** Department of Computer Science, Federal University of Technology, Minna, Nigeria.

Abdullahi, M. B., Nura, Z. M., Jiya, L. M. (2018). Examination Eligibility Verification and Attendance System Using Quick Response Code, i-manager's Journal on Digital Signal Processing, 6(3), 1-9. https://doi.org/10.26634/jdp.6.3.15681

Abstract

In many institutions, during each examination, the only requirement that is needed for a student to enter ex- amination hall is his/her identity card, which is checked for authenticity and validity of the student. This process does fail to identify if such a student is eligible to write that examination. Currently with the high ratio of students to invigilators in many examination halls, using only ID card for verification does not show whether a student registered for a subject or not. As a result, some students make use of this loophole to request the assistance of another student from another level or other department to help them sit and write the exam on their behalf. This act is impersonation and thus, is an act of examination malpractice. In this paper, an examination eligibility verification system using quick response code was developed. The EEV system was designed using UML diagrams and implemented using JavaScript, Cascading Style Sheet, and HTML5 in Microsoft Visual Studio Code for the front-end, and PHP and MySQL relational database management system for the back-end. The EEV system was validated using smart- phone to scan the QR code generated. It was observed that the system took 4 seconds to verify a student’s eligibility status. This shows that 300 students can be verified in 20 minutes. Furthermore, it provides a log file that keeps track of eligible students, which serve the purpose of attendance. So, the EEV system was friendly, secure and reliable, and has fast response time.

Privacy Preserving Classification over Encrypted Data Using Fully Homomorphic Encryption Technique

Volume 6 Issue 2 April - June 2018

Research Paper

Privacy Preserving Classification over Encrypted Data Using Fully Homomorphic Encryption Technique

Abdullahi Monday Jubrin*, Victor Onomza Waziri**, Muhammad Bashir Abdullahi***, Idris Ismaila****

*,*** Department of Computer Science, Federal University of Technology, Minna, Nigeria, and Department of Computer Science, Veritas University, Abuja, Nigeria.

**,**** Department of Cyber Security Science, Federal University of Technology Minna, Nigeria.

Jubrin, A. M., Abdullahi, M. B., Waziri, V. O., Ismaila, I. (2018). Privacy Preserving Classification Over Encrypted Data using Fully Homomorphic Encryption Technique. i-manager's Journal on Digital Signal Processing, 6(2), 36-47.https://doi.org/10.26634/jdp.6.2.15590

Abstract

Applying Machine Learning to a problem which involves medical, financial, or other types of sensitive data needs careful attention in order to maintaining data privacy and security. This paper presents a model for privacy preserving classification and demonstrated that, by using a decision tree classifier, it is possible to perform a privacy preserving classification operation on an encrypted data residing on an untrusted server using the technique of Fully Homomorphic Encryption. First, the paper presented a model for the design and implementation of privacy preserving decision tree classifier over encrypted data. Also, Fully Homomorphic Encryption technique was used to secretly carry out classification on ciphertext using decision tree model built out of confidential medical data. The classifier was implemented using the SEAL homomorphic library and evaluation was done using encrypted medical datasets. The experimental results demonstrated high accuracy of the ciphertext classifier (when compared to the plaintext data equivalent) and efficiency (compared to other classifier on similar tasks). It takes less than 5 seconds (depending on the depth) to perform classification over an encrypted hepatitis feature vector dataset.

Blockchain 3.0: Towards a Secure Ballotcoin Democracy through a Digitized Public Ledger in Developing Countries

Volume 6 Issue 2 April - June 2018

Research Paper

Blockchain 3.0: Towards a Secure Ballotcoin Democracy through a Digitized Public Ledger in Developing Countries

E. M. Dogo*, N. I. Nwulu**, O. M. Olaniyi***, C. O. Aigbavboa****, T. Nkonyana*****

*,**,***** Department of Electrical and Electronics Engineering Science, University of Johannesburg, South Africa.

*** Department of Computer Engineering, Federal University of Technology Minna, Nigeria.

**** Department of Construction Management and Quantity Survey, University of Johannesburg, South Africa.

Dogo, E. M., Nwulu, N. I., Olaniyi, O. M., Aigbavboa, C. O., Nkonyana, T. (2018). Blockchain 3.0: Towards A Secure Ballotcoin Democracy Through A Digitized Public Ledger in Developing Countries. i-manager's Journal on Digital Signal Processing, 6(2), 24-35. https://doi.org/10.26634/jdp.6.2.15593

Abstract

This paper reviews scholarly articles on the application of blockchain technology for secure electronic voting (e-voting). Furthermore, the feasibility of using blockchain technology to replace the existing manual or semidigitized voting system in developing countries with Nigeria as a case study is performed. To analyse the current state and preparedness of adopting Blockchain Enabled E-voting (BEEV) system in Nigeria, this paper employs the qualitative SWOT (Strengths, Weaknesses, Opportunities and Threats) and PEST (Political, Economic, Social and Technological) analysis approach. This evaluation leads us to identify internal and external factors and the strategic direction in adopting BEEV in Nigeria. It is the authors’ opinion that this approach could also be tailored to evaluate situations of other developing countries.

Adaptive Traffic Control System using Modified Round Robin and Genetic Algorithm

Volume 6 Issue 2 April - June 2018

Research Paper

Adaptive Traffic Control System using Modified Round Robin and Genetic Algorithm

Nasir Mohammed Sadiq*, Oluwaseun Adeniyi Ojerinde**, Solomon A. Adepoju***

*-*** Department of Computer Science, Federal University of Technology, Minna, Nigeria.

Sadiq, N. M., Ojerinde, O. A., & Adepoju, S. A. (2018). Adaptive Traffic Control System using Modified Round Robin and Genetic Algorithm. i-manager's Journal on Digital Signal Processing, 6(2), 17-23. https://doi.org/10.26634/jdp.6.2.15592

Abstract

Adaptive Traffic Control System (ATCS) serves as a main element in the constituents with which traffic control flow is achieved in fast developing, and developed urban areas. ATCS, however causes more delays on vehicles due to the fact that it is made up of intersecting points. Ensuring maximum efficiency at intersections has remained a challenge due to its dynamic nature of traffic. Additionally, a number of different methods that can be used to achieve higher performance at road traffic intersections have been recently proposed to engineers. In this study, a new and different method based on modified round robin scheduling algorithm through genetic algorithm technique to optimize the performance (in terms of timing) of a signalized intersection in one of the busiest and most crowded roads of Minna, Niger State – Nigeria (at Obasanjo shopping complex area). The technique uses an initial timing pattern to generate newer offspring (in terms of delay duration) to analyze cost function and to check if a global optimum is reached. This technique outweighs current techniques because the data upon which the nature of the system is built is relatively more phenomenal, as it puts into consideration the exact nature of the lane in many possible occurrences. In this work, a global optimum was reached at only a few number of iteration on the whole Genetic Algorithm process.

Infant Cry Recognition System using Autoregressive Model Coefficients

Volume 6 Issue 2 April - June 2018

Research Paper

Infant Cry Recognition System using Autoregressive Model Coefficients

S. R. Fatimah*, A. M. Aibinu**

* Department of Electrical Engineering, Nile University of Nigeria, Abuja, Nigeria.

** Department of Mechatronics Engineering, Federal University of Technology, Minna, Nigeria.

Fatimah, S. R., & Aibinu, A. M. (2018). Infant Cry Recognition System using Autoregressive Model Coefficients. i-manager's Journal on Digital Signal Processing, 6(2), 9-16. https://doi.org/10.26634/jdp.6.2.15591

Abstract

Understanding infants’ needs through crying is a skill acquired by health care givers as well as parents from training and experiences. However, errors may evolve due to variations in judgment and limitations on the human sensory system. Various approaches have been proposed to mimic the classical human based method which also tied results to system dominant errors. This work uses the Autoregressive (AR) model coefficient as features for recognizing infant cry. First, a dataset of infant cry consisting of Hunger, Pain and Normal cry was obtained. Each cry was framed and widowed with overlap to enable the processing of the rapidly changing cry signal. Then AR model coefficients (features) were extracted from the trained Artificial Neural Network (ANN). The extracted features were then used to train an Artificial Neural Network recognition system. The performance of this system was tested using three different activation functions, sampling frequencies and various threshold values. Results show the appropriateness of this new approach.

A Simulation Model for Cardless Automated Teller Machine Transactions

Volume 6 Issue 2 April - June 2018

Research Paper

A Simulation Model for Cardless Automated Teller Machine Transactions

O. S. Adewale*, J. O. Mebawondu**, O. J. Mebawondu***, M. N. Suleiman****

* Professor, Department of Computer Science, School of Computing, Federal University of Technology (FUTA), Akure, Nigeria.

** Principal and Lecturer, Federal Polytechnic, Nasarawa, Nasarawa State, Nigeria.

*** Senior Lecturer, Department of Computer Science, School of Information Technology, Federal Polytechnic, Nasarawa State, Nigeria.

**** Lecturer, Federal Polytechnic, Nasarawa, Nasarawa State, Nigeria.

Adewale, O. S., Mebawondu, J. O., Suleimano, M. N., & Mebawondu, J. (2018). A Simulation Model For Cardless Automated Teller Machine Transactions. i-manager's Journal on Digital Signal Processing, 6(2), 1-8. https://doi.org/10.26634/jdp.6.2.15588

Abstract

Cardless automated teller machine (CATM) is an electronic gadget that empowers the bank’s clients to perform monetary transactions such as dispensing cash to their clients, pay bills and transfer of money. The customary approach of an ATM utilizes the use of debit card for its transactions have its limitation. The challenges in utilizing such system are extortion, security and high probability of users forgetting their passwords. In this work, we propose a straightforward paradigm called CATM. The proposed CATM model used a five tuple finite machine. In the proposed platform a thumb print (Biometric) framework is utilized. The platform will improve services to clients, also secure, effective and efficient systems will be achieved.

Brief Introduction to Modular Multilevel Converters and Relative Concepts and Functionalities

Volume 6 Issue 1 January - March 2018

Survey Paper

Brief Introduction to Modular Multilevel Converters and Relative Concepts and Functionalities

Sonal Purkait*, Rahul Pandey**

* M.Tech Scholar, Department of Electrical Power System, Shri Shankaracharya Group of Institutions, Bhilai, Chhattisgarh, India.

** Assistant Professor, Department of Electrical and Electronics, Shri Shankaracharya Group of Institutions, Bhilai, Chhattisgarh, India.

Purkait, S., and Pandey, R. (2018). Brief Introduction to Modular Multilevel Converters and Relative Concepts and Functionalities. i-manager's Journal on Digital Signal Processing, 6(1), 33-39. https://doi.org/10.26634/jdp.6.1.15157

Abstract

With new developments in semiconductor technology, automation and control systems are booming. These sources have not only reduced the system size, but also allowed it to perform tasks that were impossible a few years back. Designing a DC-DC converter has always been a challenge, i.e, the way it should perform the conversion either unidirectional or bidirectional, compactness, power flow control, generation of a wide range of output levels, reduction in switching losses, etc. Among different DC-DC converters available, there is more scope for new topologies in multilevel converters. A unique multilevel converter that having striking features like high scalability, modular nature, internal fault cutback, regulation of voltage, and smaller space requirements is Modular Multilevel Converters (MMC). This paper sets an outline for studying Modular Multilevel Converters (MMC) to be applied and further developed for the wide range of applications. The later sections involve their fundamentals, modeling, control modulation, and some of the implemented applications.

A Novel Approach to Reduce Deafness in Classical Earphones: MUEAR

Volume 6 Issue 1 January - March 2018

Research Paper

A Novel Approach to Reduce Deafness in Classical Earphones: MUEAR

Gurukiran K. R. *, Gururaj H. L.**, Pavan Kumar S. P.***

* Graduate, Department of Computer Science and Engineering, Vidyavardhaka College of Engineering, Mysuru, Karnataka, India.

**-*** Assistant Professor, Department of Computer Science and Engineering, Vidyavardhaka College of Engineering, Mysuru, Karnataka, India.

Gurukiran, K. R., Gururaj, H. L., and Kumar, S. P. P. (2018). A Novel Approach to Reduce Deafness in Classical Earphones: MUEAR. i-manager's Journal on Digital Signal Processing, 6(1), 28-32. https://doi.org/10.26634/jdp.6.1.15156

Abstract

The acceptance of westernization has led to the adaptation of many new technologies effecting day to day life in positive and negative ways. One commonly seen addiction is the use of earphones. The earphones are electroacoustic transducers, which convert an electrical signal to a corresponding sound in the user's ear. Headphones are designed to allow a single user to listen to an audio source privately, in contrast to a loudspeaker, which emits sound into the open air, for anyone nearby to hear. Earphones are also known as ear speakers. These have many ill effects which would lead to deafness. This paper aims at resolving those problems using an alternate earphone, MUEAR.

Implementation of Exponential Functions on FPGA Device using Hyperbolic CORDIC Processor

Volume 6 Issue 1 January - March 2018

Research Paper

Implementation of Exponential Functions on FPGA Device using Hyperbolic CORDIC Processor

Shalini Rai*, Rajeev Srivastava**

* Research Scholar, Department of Electronics and Communication, University of Allahabad, Allahabad, India.

** Associate Professor, Department of Electronics and Communication, University of Allahabad, Allahabad, India.

Rai, S., and Srivastava, R. (2018). Implementation of Exponential Functions on FPGA Device using Hyperbolic CORDIC Processor. i-manager's Journal on Digital Signal Processing, 6(1), 21-27. https://doi.org/10.26634/jdp.6.1.15153

Abstract

In this paper, the authors illustrate the design of the exponential function based on the conventional and scale free hyperbolic Coordinate Rotation Digital Computer (CORDIC) algorithm which are used in applications of the neural networks Very Large Scale Integrated circuit design. The CORDIC algorithm is introduced to design the function of the neural networks. The design of exponential function based on conventional and scale free hyperbolic CORDIC processor is coded in VHSIC (Very High Speed Integrated Circuit) hardware description language and their simulation and synthesis results are present in this paper. The Xilinx 13.1 software is used for the simulation and synthesis of code design.