Neuronal Logic Gates Realization using CSD Algorithm

Volume 6 Issue 3 July - September 2018

Research Paper

Neuronal Logic Gates Realization using CSD Algorithm

Lakshmi kiran Mukkara*, K. Venkata Ramanaiah**

* Research Scholar, Department of Electronics and Communication Engineering, YSR Engineering College of Yogi Vemana University, Kadapa, Andhra Pradesh, India.

** Head, Department of Electronics and Communication Engineering, YSR Engineering College of Yogi Vemana University, Kadapa, Andhra Pradesh, India.

Mukkara, L. K., Ramanaiah, K. V. (2018). Neuronal Logic Gates Realization using CSD Algorithm, i-manager's Journal on Digital Signal Processing, 6(3), 18-23. https://doi.org/10.26634/jdp.6.3.15244

Abstract

Any digital circuit is made with fundamental building blocks i.e. logic gates. Artificial Neural Networks (ANN) became an emerging area in various applications such as prediction problems, pattern recognition, and robotics and system identification due to its processing capabilities with parallel architecture. Realization of Boolean logic with neural networks is referred as neuronal logic. ANN computes faster as it requires of low and simple precision computations. Also, it requires economic and low precision hardware. Neural network contains more number of addition and multiplication processes. It is known that CSD algorithm computes faster than conventional or standard multipliers. In this paper, VLSI implementation of neuronal half adder with CSD algorithm is proposed and implemented in FPGA. The results are compared with that of conventional and vedic multiplier. It is observed that CSD algorithm provides lowest delay and low power consumption in comparison with vedic algorithm and conventional method but at the expense of minimum area.