VLSI Modeling of Low Power Razor Based Programmable Truncated Multiply and Accumulator for Efficient Digital Signal Processing

Volume 5 Issue 2 April - June 2017

Research Paper

VLSI Modeling of Low Power Razor Based Programmable Truncated Multiply and Accumulator for Efficient Digital Signal Processing

M. Poornima*, P. Lokesh**, Muni Reddy.T***

*,*** Associate Professor, VEMU Institute of Technology, Chittoor, AndhraPradesh, India.

** Assistant Professor, VEMU Institute of Technology, Chittoor, AndhraPradesh, India.

Poornima.M.,Lokesh.P.,& Reddy,M.T. (2017). VLSI Modeling of Low Power Razor Based Programmable Truncated Multiply and Accumulator for Efficient Digital Signal Processing. i-manager’s Journal on Digital Signal Processing, 5(2), 31-36.https://doi.org/10.26634/jdp.5.2.13738

Abstract

In this paper the power consumption is greatly is minimized by using efficient fault Tolerant Techniques. In a VLSI architecture one has to integrate millions of circuits on printed circuit board, at the same time the designer faces difficulty to deal with the Faulty ICs incorporated in the design. The faulty chips found in the circuit that needs to be replaced earlier may lead to the damage of the circuit entirely. For this the effective fault tolerant techniques are proposed. Some of them are Design for testability, Built in Self Test, Formal verification, and Functional Verification. The VLSI is a trade-off between Design Engineer and Test Engineer. Design Engineer focuses on efficient integration of millions of transistors on a PCB whereas the role of test engineer is to find fault in the circuit. In existing architecture independent programmable truncated multipliers are used to verify fault circuits and to achieve low power consumption benefits at the output Signal to Noise Ratio. But the method suffers with delay degradation factor. In this brief, the authors use programmable Truncated multiplier within the Digital Signal Processing architecture. With this the supply voltage is minimized. This fault technique improves the performance of fault designs, and reduces error correction burden. The Simulation and Synthesis results are verified on Xilinx14.3 design suite tool with Virtex6 FPGA prototyping Hardware Environment. The design summary results show that the proposed architecture consumes less power when compared to the previous architectures.