FPGA Based Implementation of Median Filter using Compare and Exchange Unit

Volume 7 Issue 1 January - March 2019

Research Paper

FPGA Based Implementation of Median Filter using Compare and Exchange Unit

Srinu Boni*, Srinu Bevara**, Nagendra Kumar. M***

* Department of Electronics and Communication Engineering, Lendi Institute of Engineering and Technology, Vizianagaram, Andhra Pradesh, India.

** Department of Electronics and Communication Engineering, Gayatri Vidya Parishad College of Engineering (Autonomous), Visakhapatnam, Andhra Pradesh, India.

*** Department of Electronics and Communication Engineering, MVGR College of Engineering(A), Vizianagaram, Andhra Pradesh, India.

Boni, S., Bevara, S., & Kumar, N. M. (2019). FPGA Based Implementation of Median Filter using Compare and Exchange Unit i-manager’s Journal on Digital Signal Processing, 7(1), 31-35.

Abstract

Over the past few years, so many new so- lutions are gaining popularity in the software industry. All these solutions require a fast and parallel data manipulation. An attempt has been made to design median filter with high throughput and good latency to suppress the impulse based noise on real time signal and image processing applications. It is partially affected by the median filter and its bias of the input stream is directly above the average of mathematical analysis. An efficient VLSI suitable hardware implementation of a median filter is presented, that uses compare and exchange unit. The proposed hardware structure reduces the hardware requirements and has a faster processing speed, when com- pared with some other existing techniques. The input numbers or streams are used to construct an algorithm. By using this algorithm to find the median number. The proposed technique can be implemented with perfect shuffle interconnects between active stages of compare and exchange elements. In this paper all the designs are synthesized and created using MAX PLUS- II from ALTERA with fmax = 486.38MHz.