VLSI Implementation of Low Power Image Transmission Employing Modified JSCC Scheme

Volume 6 Issue 4 October - December 2018

Research Paper

VLSI Implementation of Low Power Image Transmission Employing Modified JSCC Scheme

E. Kiruba Bethesthal Elizabeth*, S. P. Valan Arasu **

*-**Department of Electronics & Communication Engineering, VV College of Engineering, Tisaiyanvilai, Tirunelveli, Tamil Nadu, India.

Elizabeth, E, K, B., and Arasu, S. V.P. (2018). VLSI Implementation of Low Power Image Transmission Employing Modified JSCC Scheme. i-manager’s Journal on Digital Signal Processing, 6(4), 20-26. https://doi.org/10.26634/jdp.6.4.16263

Abstract

Forward error correction enables reliable one- way communication over noisy channels, by transmitting redundant data along with the message in order to detect and resolve errors at the receiver. Low-density parity-check (LDPC) codes achieve superior error-correction performance on Gaussian channels, however, their complex parity-check matrix structure introduces hardware implementation challenges. Quasi-cyclic (QC) low-density parity-check (LDPC) codes form an important subclass of LDPC codes. The encoding of these codes is traditionally done by multiplying the message vector with a generator matrix consisting of dense circulant submatrices. To reduce the encoder complexity a new scheme is introduced by making use of finite fourier transform .Making use of conjugacy constraints, low complexity architectures are developed for finite fourier and inverse transforms over subfields. In addition composite field arithmetic is exploited to eliminate the computations associated with message mapping and to reduce the complexity of Fourier transform. Since the proposed encoder has much improvement in power consumption and reduction in area than the conventional encoders, it is considered to be an efficient QC-LDPC encoder.