Automatic Traffic Management System for Emergency Vehicles

Volume 7 Issue 1 January - March 2019

Technical Column

Automatic Traffic Management System for Emergency Vehicles

Jamuna*, Vinay M. G.**

*-** Department of Computer Science and Engineering, Vidyavardhaka College of Engineering, Mysuru, Karnataka, India.

Jamuna and Vinay, M. G., (2019). Automatic Traffic Management System for Emergency Vehicles. i-manager’s Journal on Digital Signal Processing, 7(1), 36-42.

Abstract

One of the major problems faced by people in their daily life is traffic. An efficient management system is required to provide efficient traffic control system. Identification of particular vehicle in the traffic flow is a notable task in the traffic management system. In this project, we propose an automatic traffic management system for vehicle detection and counting and automatic signals scheduling. The camera supplies video input to the processing engine. Initially the video will be streaming on all four roads of the traffic circle. The values will be read frame by frame in the streaming video of these roads. Camera sends all the captured input images to the processing engine and this works based on the neural network. The traffic flow shows the traffic state in fixed time interval and helps to manage and control the traffic especially when there is a heavy traffic and will consider emergency vehicles like ambulance and fire brigades, giving them priority togo.

FPGA Based Implementation of Median Filter using Compare and Exchange Unit

Volume 7 Issue 1 January - March 2019

Research Paper

FPGA Based Implementation of Median Filter using Compare and Exchange Unit

Srinu Boni*, Srinu Bevara**, Nagendra Kumar. M***

* Department of Electronics and Communication Engineering, Lendi Institute of Engineering and Technology, Vizianagaram, Andhra Pradesh, India.

** Department of Electronics and Communication Engineering, Gayatri Vidya Parishad College of Engineering (Autonomous), Visakhapatnam, Andhra Pradesh, India.

*** Department of Electronics and Communication Engineering, MVGR College of Engineering(A), Vizianagaram, Andhra Pradesh, India.

Boni, S., Bevara, S., & Kumar, N. M. (2019). FPGA Based Implementation of Median Filter using Compare and Exchange Unit i-manager’s Journal on Digital Signal Processing, 7(1), 31-35.

Abstract

Over the past few years, so many new so- lutions are gaining popularity in the software industry. All these solutions require a fast and parallel data manipulation. An attempt has been made to design median filter with high throughput and good latency to suppress the impulse based noise on real time signal and image processing applications. It is partially affected by the median filter and its bias of the input stream is directly above the average of mathematical analysis. An efficient VLSI suitable hardware implementation of a median filter is presented, that uses compare and exchange unit. The proposed hardware structure reduces the hardware requirements and has a faster processing speed, when com- pared with some other existing techniques. The input numbers or streams are used to construct an algorithm. By using this algorithm to find the median number. The proposed technique can be implemented with perfect shuffle interconnects between active stages of compare and exchange elements. In this paper all the designs are synthesized and created using MAX PLUS- II from ALTERA with fmax = 486.38MHz.

Developing Sidelobe Reduction Techniques using P4 Code for Pulse Compression Radar Applications

Volume 7 Issue 1 January - March 2019

Research Paper

Developing Sidelobe Reduction Techniques using P4 Code for Pulse Compression Radar Applications

CH. RamyaSree*, G.H. Sindhuja**, A.V. Sai Kumar***, G. Sri Harsha****, B. Kiranmai*****

*_***** Department of Electronics and Communication Engineering, Lendi Institute of Engineering and Technology, Vizianagaram, Andhra Pradesh, India.

Sree, R., Sindhuja, G. H., Kumar, A. V. S., Harsha, G. S., & Kiranmani, B. (2019). Developing Sidelobe Reduction Techniques using P4 Code for Pulse Compression Radar Applications i-manager’s Journal on Digital Signal Processing, 7(1), 25-30.

Abstract

This paper present a novel technique for the ‘reduction of the side-lobes in the pulse compression (PC)’ for the radar systems. This pulse compression increases the range resolution and signal to noise ratio. The peak sidelobe ratio and signal noise reduction loss are computed using P4 polyphase codes. This result is compared with various weighting techniques applied on the output of Woo filter in order to suppress the side lobes. This proposed PC technique is implemented by shifting the input P4 polyphase codes and multiplied it with reference signal. This technique produces certain improvement in Peak Sidelobe Ratio and Signal Noise Reduction Loss(SNR Loss).

Speed Enhancement of Modified Booths Encoding Algorithm Using Verilog HDL

Volume 7 Issue 1 January - March 2019

Research Paper

Speed Enhancement of Modified Booths Encoding Algorithm Using Verilog HDL

Gopi Chand Naguboina*, T. Sravya**

* Department of Electronics and Communication Engineering, MVGR College of Engineering(A), Vizianagaram, AndhraPradesh India.

** Department of Electrical and Electronics Engineering, Lendi Institute of Engineering and Technology, Vizianagaram, AndhraPradesh, India.

Naguboina, G. C., & Sravya. T. (2019). Speed Enhancement of Modified Booths Encoding Algorithm Using Verilog HDL. i-manager’s Journal on Digital Signal Processing, 7(1), 20-24.

Abstract

This paper presents the design and implementation of Modified Booths encoding algorithm with enhanced speed. Multiplication is the most commonly used operation in every step of arithmetic. The speed of multiplier determines the speed of processor. So, there is a need for high speed multiplier. Adders play a dominant role in arithmetic addition of partial products. Increase in the speed of any arithmetic operation results in the increase of speed of overall operation of multiplier. So the main focus in this paper is to increase the speed of adder in turn increasing the speed of multiplication process. An algorithm is proposed using Modified Booths algorithm, Wallace tree structure and Kogge-Stone adder design. MBE reduces the number of partial products and has least latency compared to other multiplier algorithms. Wallace tree structure increases the speed of accumulation of partial products. A Kogge-Stone adder design is used in the multiplier design which yields to reduced delay and area. The proposed Modified Booth Multiplier design shows better performance compared to that of the conventional method using Kogge-Stone Adder and has advantages of reduced area overhead and critical path delay. The proposed design has been synthesized using Xilinx ISE 14.2 design tool using Verilog HDL.

Design of Y Shaped 2x1 Encoder using Two Dimensional Photonic Crystals

Volume 7 Issue 1 January - March 2019

Research Paper

Design of Y Shaped 2x1 Encoder using Two Dimensional Photonic Crystals

K. Latha*, R. Arunkumar**, S. Robinson***

*_*** Department of Electronics and Communication and Engineering, Mount Zion College of Engineering and Technology, Pudukkottai, Tamilnadu, India.

Latha, K., Arunkumar, R., & Robinson, S. (2019). Design of Y Shaped 2x1 Encoder using Two Dimensional Photonic Crystals. i-manager’s Journal on Digital Signal Processing, 7(1), 11-19.

Abstract

In this Y shaped 2x1 encoder design is based on two dimensional photonic crystals. And this encoder design is constructed by point and line defects of photonic crystal which is providing high contrast ratio and reduced power loss for proposed design. The performances field distributions are analyzed finite difference time domain and the band structures are evaluated plane wave expansion method. The proposed 2x1 encoder operated at 1520nm and it provides contrast ratio of 28dB, response time of 3.9ps and bit rate of around 0.25Tbps. So, it is suitable for photonic integrated circuits.

Airbase Detection and Airship Recognition in High Spatial Resolution Remote Sensing Images

Volume 7 Issue 1 January - March 2019

Research Paper

Airbase Detection and Airship Recognition in High Spatial Resolution Remote Sensing Images

B. Bersi Beulah*

Department of Electronics and Communication and Engineering, PET Engineering College, Tirunelveli, Tamil Nadu, India.

Beulah, B. B. (2019). Airbase Detection and Airship Recognition in High Spatial Resolution Remote Sensing Images. i-manager’s Journal on Digital Signal Processing, 7(1),1-10.

Abstract

In the proposed work two-layer visual saliency analysis model and support vector machines (SVMs) are used for Airport detection and Aircraft Recognition. In the first layer saliency (FLS) model, introduce a spatial-frequency visual saliency analysis algorithm that is based on a CIE Lab color space to reduce the interference of backgrounds and efficiently detect well-defined airport regions in broad-area remote-sensing images. In the second layer saliency model, propose a saliency analysis strategy that is based on an edge feature preserving wavelet transform and high-frequency wavelet coefficient reconstruction to complete the preextraction of aircraft candidates from airport regions that are detected by the FLS and crudely extract as many aircraft candidates as possible for additional classification in detected airport regions. Then, utilize feature descriptors that are based on a dense SIFT and Hu moment to accurately describe these features of the aircraft candidates. Finally, these object features are inputted to the SVM, and the aircraft are recognized. The experimental results indicate that the proposed method not only reliably and effectively detects targets in high-resolution broad-area remotesensing images but also produces more robust results in complex scenes.

Internet of Things (IoT) Based Home Automation: A Review

Volume 6 Issue 4 October - December 2018

Review Paper

Internet of Things (IoT) Based Home Automation: A Review

Nidhi Singh*, Ankita Sharma **, Anurag Dwivedi ***, Nitesh Tiwari ****

*-**** Department of Electrical Engineering, KIPM College of Engineering & Technology, Gorakhpur Industrial Development Authority, Gorakhpur, Uttar Pradesh, India.

Singh, N., Sharma, A., Dwivedi, A., and Tiwari, N. (2018). Internet of Things (IoT) Based Home Automation: A Review. i-manager’s Journal on Digital Signal Processing, 6(4), 34-41. https://doi.org/10.26634/jdp.6.4.15955

Abstract

The recent decade has experienced revolution of smart technology with the introduction of smartphones and electronic equipments in day to day life as an important part of life. IoT (Internet of Things) can be defined as human connecting object like sensors, internet TVs, smartphones and actuators with the internet where electronic devices are linked together intelligently enabling new shell of communication between people and electronic devices, and between devices themselves. IoT is presented with the overview to begin the idea of a smart home with its security and the necessity of software and hardware components for making a smart home.